The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure that includes an nFET nanosheet stack of suspended silicon channel material nanosheets in an nFET device region and a pFET nanosheet stack of suspended silicon germanium alloy channel material nanosheets in a pFET device region, wherein each silicon channel material nanosheet in the nFET device region is off-set by one nanosheet from each silicon germanium alloy channel material nanosheet in the pFET device region.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs) is the next step in the evolution of CMOS devices. One type of non-planar semiconductor device that has been touted as a viable option beyond the 7 nm technology node is a nanosheet containing device. Nanosheet formation relies on the selective removal of one semiconductor material relative to another semiconductor material to form suspended nanosheets for gate-all-around devices. In current nanosheet CMOS processing, silicon is used as the channel material for both the nFET device region and the pFET device region due to process complexity induced by an additional patterning step in the epitaxial channel stack formation.
A silicon germanium alloy material is one promising candidate for use as a semiconductor channel material nanosheet for pFET devices since it provides more flexibility in pFET threshold voltage design, and has improved pFET reliability as compared with a pFET device including a silicon channel material. Dual semiconductor channel material nanostacks are needed in which the pFET device region includes a vertical stack of suspended silicon germanium alloy channel material nanostacks, while the nFET device region includes a vertical stack of suspended silicon channel material nanostacks.